Verification of Authenticated Firmware Load

An important primitive in ensuring security of modern systems-on-chip designs are protocols for authenticated firmware load. These loaders read a firmware binary image from an untrusted input device, authenticate the image using cryptography and load the image into memory for execution if authentication succeeds. While these protocols are an essential part of the hardware root of trust in almost all modern computing devices, verification techniques for reasoning about end-to-end security of these protocols do not exist. This paper takes a step toward addressing this gap by introducing a system model, adversary model and end-to-end security property that enable reasoning about the security of authenticated load protocols. We then present a decomposition of the security hyperproperty into two simpler 2-safety properties that enables more scalable verification. Experiments on a protocol model demonstrate viability of the methodology

Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors

Relentless scaling of CMOS fabrication technology has made contemporary integrated circuits increasingly susceptible to transient faults, wearout-related permanent faults, intermittent faults and process variations. Therefore, mechanisms to mitigate the effects of decreased reliability are expected to become essential components of future general­ purpose microprocessors. In this paper, we introduce a new throughput-efficient architecture for multiplexed fault-tolerant chip multiprocessors (CMPs). Our proposal relies on the new technique of adaptive execution assistance, which dynamically varies instruction outcomes forwarded from the leading core to the trailing core based on measures of trailing core performance. We identify policies and design low overhead hardware mechanisms to achieve this. Our work also introduces a new priority-based thread-scheduling algorithm for multiplexed architectures that improves multiplexed fault­ tolerant CMP throughput by prioritizing stalled threads. Through simulation-based evaluation, we find that our proposal delivers 17.2% higher throughput than perfect dual modular redundant (DMR) execution and outperforms previous proposals for throughput-efficient CMP architectures

Electromagnetic Transmission of Intellectual Property Data to Protect FPGA Designs

International audienceOver the past 10 years, the designers of intellectual properties(IP) have faced increasing threats including cloning, counterfeiting, andreverse-engineering. This is now a critical issue for the microelectronicsindustry. The design of a secure, efficient, lightweight protection scheme fordesign data is a serious challenge for the hardware security community. In thiscontext, this chapter presents two ultra-lightweight transmitters using sidechannel leakage based on electromagnetic emanation to send embedded IPidentity discreetly and quickl

Deriving Abstractions to Address Hardware Platform Security Challenges

Today's computing devices store and process an enormous amount of security-critical assets. These assets are a lucrative target for cybercriminals and protecting them from malicious actors remains a key challenge in computer security. Hardware is especially important in this context: security protections implemented in software may be invalidated by faulty hardware. Ensuring hardware remains secure is becoming difficult. Deverticalization and globalization of the semiconductor industry have led to the separation of integrated circuit (IC) design houses from foundries and rendered ICs vulnerable to the threat of malicious design changes, i.e., hardware trojans. The emergence of systems-on-chip (SoC) designs, which comprise multiple programmable cores, firmware and application-specific accelerators, poses new verification challenges. In particular, verifying that SoC security requirements are met is challenging due to the need for co-verification of firmware and hardware. This thesis first tackles the problem of algorithmic reverse engineering of digital circuits which can help analysts detect hardware trojans. We present a comprehensive portfolio of algorithms which analyze a flat unstructured netlist and output a high-level netlist with components such as register files, counters, adders and subtracters. Our techniques are fully-automated and scalable to designs with hundreds of thousands of gates. Next, we present a methodology for system-level security verification of SoCs. The methodology is based on the construction of instruction-level abstractions (ILA). The ILA raises the level of abstraction of hardware modules to be similar to that of instructions in programmable processors. It can be used instead of the cycle-accurate and bit-precise hardware description for scalable co-verification of system-level security properties in SoCs. We introduce techniques to semi-automatically synthesize the ILA and show how it can be proven to be a correct abstraction of the underlying hardware. We then show how the ILA is used for security verification by designing a specification language and verification algorithm for information-flow properties. In summary, this thesis presents a set of techniques to address security challenges in modern SoCs. In particular, it provides a methodology for verifying security of SoCs where security properties hold for the complete system, not just individual components such as the hardware or firmware alone

Energy-Efficient Fault Tolerance in Chip Multiprocessors Using Critical Value Forwarding

Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chip fault tolerance in future chip microprocessors (CMPs). In this paper we introduce a new energy-efficient fault-tolerant CMP architecture known as Redundant Execution using Critical Value Forwarding (RECVF). RECVF is based on two observations: (i) forwarding critical instruction results from the leading to the trailing core enables the latter to execute faster, and (ii) this speedup can be exploited to reduce energy consumption by operating the trailing core at a lower voltage-frequency level. Our evaluation shows that RECVF consumes 37% less energy than conventional dual modular redundant (DMR) execution of a program. It consumes only 1.26 times the energy of a nonfault- tolerant baseline and has a performance overhead of just 1.2%.©2010 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. Pramod Subramanyan, Virendra Singh, Kewal K. Saluja and Erik Larsson, Energy-Efficient Fault Tolerance in Chip Multiprocessors Using Critical Value Forwarding, 2010, The 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'10), Fairmont Chicago, Millennium Park, Chicago, Illinois, USA, June 28-July 1, 2010, 121-130.</p

A Formal Approach to Secure Speculation.

Transient execution attacks like Spectre, Meltdown and Foreshadow have shown that combinations of microarchitectural side-channels can be synergistically exploited to create side-channel leaks that are greater than the sum of their parts. While both hardware and software mitigations have been proposed against these attacks, provable security has remained elusive. This paper introduces a formal methodology for enabling secure speculative execution on modern processors. We propose a new class of of information flow security properties called trace property-dependent observational determinism (TPOD). We use this class to formulate a secure speculation property. Our formulation precisely characterises all transient execution vulnerabilities. We demonstrate its applicability by verifying secure speculation for several illustrative programs

Energy-efficient redundant execution for chip multiprocessors

Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chip fault tolerance in future chip microprocessors (CMPs). In this paper, we describe a power-efficient architecture for redundant execution on chip multiprocessors (CMPs) which when coupled with our per-core dynamic voltage and frequency scaling (DVFS) algorithm significantly reduces the energy overhead of redundant execution without sacrificing performance. Our evaluation shows that this architecture has a performance overhead of only 0.3% and consumes only 1.48 times the energy of a non-fault-tolerant baseline